1. Field of the Invention
The present invention relates to a technique to suppress an electromagnetic radiation noise, and more particularly to a switching noise suppression circuit to suppress a switching noise of a circuit in which an activation and a inactivation are repeated by an enable signal, a built-in noise filter type data holding circuit in which this switching noise suppression circuit is built, a car navigation apparatus which comprises this built-in noise filter type data holding circuit, a communication circuit for sending and receiving a digital signal through data buses and a communication apparatus which comprises this circuit. Moreover, the present invention relates to a technique to suppress an electromagnetic radiation noise in an application-specific integrated circuit (ASIC).
2. Description of the Related Art
Recently, an environment problem of an electromagnetic radiation has been largely taken up. The generation of an EMI (electromagnetic interference) noise may cause another electronic apparatus to be erroneously operated, which may result in a serious trouble.
The EMI noise is roughly classified into the three basic types listed below:                (1) a conduction noise from a power supply line;        (2) a leakage noise from a port; and        (3) a radiation noise from an LSI surface.        
The (1) conduction noise from the power supply line depends on a waveform of a power supply current, and is conducted/radiated with the power supply line as an antenna. In a case of the (2) leakage noise from the port, a change of a potential of the power supply is conducted/radiated from a pin of an LSI, such as a port and the like, with an external wire as an antenna. The (3) radiation noise from the LSI surface is mainly radiated from the LSI surface to space with a current loop as an antenna.
Among them, the conduction noise from the power supply line has the largest possibility of having a bad influence on other electronic apparatuses. Thus, the counter-plan thereof is of urgent necessity. As for this conduction noise from the power supply line, a change of a signal inputted to a circuit causes the power supply current to be changed, which results in the generation of the noise. This is typically referred to as a switching noise. Conventionally, an RC filter is inserted as shown in FIG. 1, in order to suppress such a switching noise.
In FIG. 1, a capacitor C is referred to as “a bypass capacitor”, and a resistor R is referred to as “a limiter resistor”. For example, the bypass capacitor C is made of the gate capacitance of transistors constituting an LSI. The limiter resistor R is made of a polysilicon-resistor or an aluminum resistor which is mounted on the predetermined portions of a semiconductor chip constituting the LSI. Moreover, in FIG. 1, an enable signal GN is a signal based on a clock signal, and an internal circuit 101 is constituted by, for example, a latch.
FIGS. 2A to 2D are views of showing waves at respective nodes when the circuit shown in FIG. 1 is simulated by using simulation program with integrated circuit emphasis (SPICE). Then, FIG. 2A shows a voltage waveform of the enable signal GN, FIG. 2B shows a voltage waveform of an input signal DIN, FIG. 2C shows a voltage waveform of an output signal Q and FIG. 2D shows a current waveform of a high level power supply line VDD.
When the enable signal GN is triggered to the internal circuit 101 connected to the high level power supply line VDD, the power supply current flows. If the activation current GN is similarly repeated for each constant period as shown in FIG. 2A, the power supply current also has a constant period as can be seen from FIG. 2D. An electromagnetic wave radiated by this power supply current can be determined by using the Maxwell equations. However, a noise analysis is usually performed by performing a Fourier analysis on the power supply current and using a spectrum represented as a transmission amount (dB) to a reference value for each frequency.
FIG. 3 shows the spectrum to the power supply current shown in FIG. 2D. A reference value of a noise level shown on a vertical axis in FIG. 3 is assumed to be 1 A. Hereafter, a reference value is assumed to be 1 A when the spectrum of the noise is similarly shown. It is presumed that a smaller transmission amount (dB) has a lower noise level. Similarly, the power of a radiation can be represented by using the spectrum. However, it is omitted.
In FIG. 1, when the enable signal GN is triggered and the internal circuit 101 is operated, a current is supplied from the high level power supply line VDD and further a current is supplied from charges accumulated in the bypass capacitor C. At this time, the current running through the high level power supply line VDD is limited by the limiter resistor R. Thus, the sudden change of the power supply current becomes small. This results in the reduction of the noise level as compared with a case having no RC filter.
In the prior art shown in FIG. 1, the noise filter constituted by the limiter resistor R and the bypass capacitor C as shown in FIG. 1 is used to suppress the switching noise. However, especially, since many latches used in an integrated circuit are simultaneously operated in synchronization with a clock, the power supply current suddenly flows to thereby generate the switching noise. At this time, if the capacitance of the bypass capacitor C is small and a load current is large, the switching noise may exceed an allowable value.
That is, in the conventional configuration in FIG. 1, the load current consumed by the internal circuit 101 is directly supplied from the high level power supply line VDD to thereby cause the sudden flow of the power supply current. Hence, it is necessary to mount the bypass capacitor C having a large capacitance in order to sufficiently suppress the switching noise generated at that time.
However, it is conventionally difficult to insert the bypass capacitor having the large capacitance in the view of a limitation of a chip area, a cost and the like when the RC filter is inserted into the chip of the LSI. After all, the consideration of the chip area and the cost leads to the unavoidable utilization of the bypass capacitor having the small capacitance for them. In this case, it is very difficult to sufficiently suppress the switching noise generated by the sudden change of the power supply current. In the present condition, it is also impossible to deal with the generation of the switching noise which exceeds the allowable value.
Incidentally, a semicustom design methodology of using a gate array and a standard cell has been mainly used as an approach of designing the LSI in order to respond to a requirement of shortening a turn around time (TAT) of a product and a system. In the gate array, as shown in FIG. 4A, a master chip in which basic cells 201 composed of a plurality of transistors are arranged in a form of a grid is made in advance, and then any metal interconnect is disposed on the master chip in accordance with a request of a client. The gate array has a feature of shortening the TAT of the chip, since various logic circuits can be formed only by changing the metal layer.
The conventional basic cells 201u and 201l shown in FIG. 4A have two n channel MOS transistors (hereafter, referred to as an nMOS transistor) and two p channel MOS transistors (hereafter, referred to as a pMOS transistor), respectively. A substrate contact region 202 is formed between the upper basic cell 201u and lower basic cell 201l. Contact holes are formed on this substrate contact region 202 to establish the ohmic contact between the metal interconnect on an upper level and the well region on a lower level. A signal line, a ground line and the power supply line are wired with the metal interconnect (conductive layer) on the upper level such as an aluminum layer and the like, although they are not shown in FIG. 4A.
On the other hand, in a cell base LSI, standard cells having a desired logic function are formed in advance on a wafer, and a chip is formed by combining these standard cells in accordance with a request of a client. FIG. 4B shows an example of a layout of a standard cell. The standard cell 261 is composed an nMOS transistor region 262 having the two nMOS transistors and a pMOS transistor region 263 having the two pMOS transistors. A substrate contact region 202 is formed between the adjacent standard cells similarly to FIG. 4A. In the semicustom design methodology of using the gate array and the standard cell as mentioned above, the connection between the signal line, the ground line and the power supply line can be selectively performed by using a CAD tool and the like.
The above mentioned EMI noise is generated even in the LSI manufactured by using the semicustom architecture of using the gate array, the standard cell and the like. Accordingly, other electronic apparatuses may be erroneously operated by the EMI noise generated in the semicustom LSI. For this reason, conventionally, the suppression of the EMI noise is tried by disposing the RC filter similar to that of FIG. 1 within the chip or outside an LSI package.
In the gate array and the standard cell architectures, the bypass capacitor C is formed by using a gate oxide film of a transistor, and the limiter resistor R is formed by using a doped polysilicon resistor or an aluminum resistor. In the semicustom LSI, it is easy to form the bypass capacitor by using the gate oxide film of the transistor. However, the capacitance of the bypass capacitor per unit area on a device formation surface can not be made so large. Moreover, many transistors are required in order to form a desired capacitance of the bypass capacitor. For this reason, the capacitance necessary for the noise filter can not be obtained, and further the switching noise can not be sufficiently suppressed. That is, this implies that it is impossible to attain the sufficient effect for the suppression of the EMI noise.
On the other hand, in a case of designing the LSI chip, a synchronization circuit synchronizing with a system clock inputted from the exterior is typically designed in order to protect against a timing obstacle. For this reason, numerous flip-flops and numerous clock buffer cells which are operated on the basis of the clock are mounted within the LSI chip. In these flip-flops and clock buffer cells, a switching is brought about within the flip-flop on the basis of the logic of the clock. If a large current is dynamically consumed as mentioned above, the change of the current is observed as the EMI noise at the exterior through the parasitic inductance of the chip.
In order to suppress the EMI noise, two counter-plans listed below are effective:
(a) A first counter-plan is a method of reducing the power dissipation to thereby reduce the change of the current which causes the generation of the noise; and
(b) A second counter-plan is a method of mounting numerous bypass capacitors on a chip so that the change of the power supply voltage becomes small.
The former will be described later. As for the latter, a method in which the bypass capacitor is formed within the LSI chip and then the transient change of the electric power is absorbed by the bypass capacitor is proposed in the cell-base LSI. However, basic cells 1 having predetermined structures are mounted on a whole surface, in the LSI of the master slice type, such as the gate array and the like. These basic cells 1 are used to form a logic circuit. Hence, it is technically difficult to freely form the bypass capacitor cells on the chip. Now, there is no method to effectively suppress the EMI noise.
Incidentally, the advancement of the semiconductor process technique enables memories, such as DRAM and the like, to be mixed and mounted on the gate array and the standard cell. For example, FIG. 5A is a schematic layout of showing an example of a chip on which a gate array 111 and a DRAM macro cell 112 are mixed and mounted. FIG. 5B is a schematic layout of showing an example of a chip on which cell columns 103 of standard cells metal interconnects 104 and the DRAM cell 112 are mixed and mounted. In the DRAM macro cell 112, a memory cell is composed of a transistor and a capacitor. In short, the capacitor is located at each memory cell. The miniaturization of the size of the memory cell is required in conjunction with the DRAM having a larger capacitance. Typically, the capacitor is manufactured by a trench process and the like in order to make the capacitance larger.
FIG. 6 is a sectional view of a capacitor C constituting the memory cell of the DRAM manufactured by the trench process. A diffusion layer 105 is formed along a side wall of a trench (groove), an insulator layer 106 is formed on a top surface of the diffusion layer 105, and a doped polysilicon layer 107 is formed on a top layer of the insulator layer 106. The capacitor C is constituted by the diffusion layer 105, the insulator layer 106 and the doped polysilicon layer 107. Then, charges are accumulated in the portion of the insulator layer 106. The capacitance sufficient to store data for each memory cell can be obtained by making the groove deeper and accordingly making the area of the side wall larger.
As mentioned above, the capacitor having the trench structure can obtain the large capacitance with a small area. However, there is no attempt of using this type capacitor as the bypass capacitor to suppress the noise.
Next, a method of reducing the current change which causes the noise will be explained with a data bus as an example. If the currents having the same direction simultaneously run through many signal lines of the data buses, a strong EMI noise is generated. In a logic gate composed of a CMOS transistor circuit, an operational current which occurs in a simultaneous switching and runs out from a power supply line or runs into a ground line becomes the largest when all outputs of the logic gate are at a high level or a low level. If such an operational current is large, the large operational current runs through a parasitic resister and a parasitic inductance to thereby make the generated voltage drop larger. As a result, it is difficult to insure the stable operation of the circuit.
For example, a technique disclosed in Japanese Patent Application Laying Open (KOKAI) No.59-212027 is well known as the prior art to solve the above mentioned defects. And, a technique disclosed in a document shown in FIGS. 7A to 7C is also well known which is entitled “Noise Suppression Scheme for Giga-Scale DRAM with Hundred of I/Os” written by Daizaburo Takashima., et al., and published in Technical Report of Electronic Information Communication Society, SDM96-73, ICD96-93 (1996–08) pp. 43–46.
In such a prior art, for example, when data of 64 bits is sent and received, the data of 64 bits is divided into even-numbered blocks, for example, four blocks as shown in FIG. 8, and a flag bit is established for each two blocks. In such a state, an absolute value of a difference between the numbers of “0” and “1” is calculated for the data at each block. If the absolute values are larger than 16, or a half of 32, in a block 0 and a block 1 all in all, the flag bits corresponding to the block 0 and the block 1 are inverted from 0 to 1. All the data at the block 1 are inverted from “0” to “1”, encoded and outputted to the data bus. The same process is performed in a block 2 and a block 3.
If data of four bits, for example, (1, 1, 1, 1) is sent and received through a data bus 123 of four bits between a sender chip 121 and a receiver chip 122 as shown in FIG. 9A, the data of four bits is divided into two blocks composed of data of two bits. Then, the data (1, 1) at one block is inverted to (0, 0) and encoded by an encoder 124, the flag bit is inverted from 0 to 1, the encoded data and flag bit are sent through the data bus 123, and the sent data is decoded to the original data of four bits by a decoder 125. In this way, the numbers of “0” and “1” sent through the data bus are made equal to each other to thereby suppress the above mentioned noise.
However, in such a prior art, the flag bits are required by a half of the number of the divided blocks. Thus, the number of the data buses is increased as the number of the bits of the data to be sent is increased. When the number of the bits of the data to be sent is increased, even if data at part of the blocks is inverted, there may be a case that the numbers of “0” and “1” are not equal to each other in all the data. Hence, in order to reduce the difference between the numbers of “0” and “1” to make the numbers substantially equal to each other, the data to be sent must be divided into many blocks.
As explained above, in the conventional method of sending and receiving the digital signal in which a common phase power supply noise is suppressed, it is necessary to divide the data to be sent into many blocks to then establish the flag bits at the respective blocks, in order to improve the suppression effect. For this reason, numerous flag bits are required. Thus, the buses to send and receive the flag bits are required in addition to the buses corresponding to the number of the bits of the data to be sent and received. This results in the problem of the increase of the number of the data buses.